Post-quantum cryptographic and hardware security IP enables chipmakers to integrate quantum-safe key determination, digital signatures, secure boot and device trust directly into RISC-V-based silicon
NEW DELHI, June 18, 2026 /PRNewswire/ — Synergy Quantum today announced a portfolio of quantum-safe silicon IP cores for RISC-V-based system-on-chip designsallowing semiconductor companies, processor developers and equipment manufacturers to integrate post-quantum cryptographic capabilities directly into ASICs, FPGAs and embedded platforms. The IP portfolio, developed by Synergy Quantum, combines post-quantum cryptographic acceleration with secure boot, hardware-based identity, secure key processing, firmware authentication and device attestation capabilities.
The portfolio is designed for integration into RISC-V-based SoCs as dedicated security components, cryptographic coprocessors, or building blocks within a broader hardware root-of-trust subsystem. By putting quantum-safe cryptographic functions directly into silicon, the architecture can improve performance, reduce reliance on software-only implementations, and provide stronger isolation for sensitive keys and intermediate cryptographic values.
Bringing quantum-safe security to RISC-V silicon
RISC-V is increasingly being used in embedded systems, industrial platforms, communications infrastructure, defense electronics, automotive systems and custom semiconductor designs. Many of these devices are expected to remain operational for years or even decades. Their security architectures must therefore be able to support the transition from classical cryptography to post-quantum security.
Synergy Quantum’s silicon IP portfolio aims to help RISC-V developers address this transition at the processor and SoC level. Rather than treating post-quantum cryptography as an application layer upgrade, the IP makes it possible to implement keys, signature verification, secure boot, and device trust as dedicated hardware functions within the chip. The architecture supports industry-standard SoC interconnects and processor expansion interfaces, allowing the cores to be integrated with existing RISC-V processors and custom SoC architectures without requiring a complete redesign of the host platform.
Quantum-safe IP developed for hardware integration
The Synergy Quantum portfolio includes silicon IP and accelerator architectures that support:
- ML-KEM based post-quantum key determination.
- ML-DSA based post-quantum digital signatures.
- SLH-DSA and LMS-based hash signature architectures.
- HQC-based algorithm diversity.
- SHA-3 and Keccak cryptographic processing.
- Ascon authenticated encryption.
- Shared number-theoretic transformation acceleration.
- Safe and measured start-up.
- Post-quantum firmware signature verification.
- Hardware-enforced rollback protection.
- PUF-derived device identity.
- DICE style device certificate.
- Protected key diversion and key seal.
- Hybrid classical and post-quantum surgery.
The IP address can be configured based on the performance, power, silicon area, and security requirements of the target application.
Deployments can range from compact, low-power cryptographic blocks for embedded and IoT devices to higher throughput accelerators for telecom, networking, data center and security applications.
A configurable RISC-V security architecture
The portfolio combines programmable RISC-V control with dedicated cryptographic hardware.
This model allows security policies, protocol handling, and device-specific logic to be managed through software or firmware, while performing compute-intensive and security-sensitive operations within isolated hardware data paths.
The architecture can support:
- Post-quantum key establishment and authentication.
- Secure firmware and software updates.
- Quantum safe, secure boot.
- Device onboarding and machine identity.
- Remote device attestation.
- Hardware-secure signing and authentication.
- Secure communication and VPN acceleration.
- TLS and embedded network security protocols.
- Secure key release for authorized firmware or workloads.
The IP cores can be integrated individually or combined into a complete quantum-safe security subsystem.
This gives SoC developers the flexibility to adopt the capabilities needed for a given product, while maintaining a path to broader hardware-based security.
Designed for crypto flexibility
The post-quantum transition will continue to evolve as standards, implementation guidelines, and security research evolve.
For semiconductor products with long life cycles, the ability to update cryptographic algorithms and policies is therefore essential.
Synergy Quantum’s architecture is designed to support crypto flexibility through reusable calculators, shared cryptographic data paths, and programmable security control.
Shared NTT and Keccak processing components can be used in multiple lattice-based cryptographic algorithms. This reduces unnecessary hardware duplication and allows multiple cryptographic functions to operate within a common silicon architecture.
Select configurations can also support controlled cryptographic updates and hardware-enforced anti-rollback mechanisms, allowing manufacturers to respond to future changes without replacing the entire device architecture.
This enables a phased migration path from classical cryptography to hybrid implementations and ultimately to fully post-quantum operations.
Protection against deployment-level attacks
Mathematical resistance to quantum attacks is only one part of hardware security.
Physical implementations must also consider timing attacks, power analysis, electromagnetic analysis, fault injection, and attempts to retrieve keys from memory or internal data paths.
Synergy Quantum’s quantum-safe IP architecture includes options for:
- Constant-time cryptographic execution.
- Masked arithmetic for sensitive operations.
- Isolated generation and renewal of masking values.
- Protected processing of intermediate cryptographic values.
- Hardware-enforced operation order.
- Safe zeroing of temporary key material.
- PUF-bound key derivation.
- Secure measurement of boot status.
- Firmware anti-rollback enforcement.
- Manipulation-aware attestation workflows.
These capabilities are designed for products that may operate in hostile, physically accessible, or mission-critical environments.
Supporting semiconductor and system developers
The Synergy Quantum IP portfolio is intended for:
- RISC-V processor and SoC developers.
- Semiconductor manufacturers and design houses.
- Foundries and partners in the semiconductor ecosystem.
- FPGA-based product developers.
- Defense and aerospace electronics companies.
- Manufacturers of telecom and networking equipment.
- Suppliers of industrial and operational technology.
- Developers of automotive and autonomous systems.
- Manufacturers of IoT and embedded devices.
- Suppliers of cloud, data center and security equipment.
The cores can be integrated into secure processors, network controllers, communications equipment, gateways, firewalls, hardware security platforms, industrial controllers, satellite systems and long-life connected devices.
In addition to the SynQ Silicon Trust Suite
The quantum-safe RISC-V silicon IP portfolio complements the previously announced Synergy Quantum SynQ Silicon Trust Suite. The SynQ Silicon Trust Suite provides the broader system-level framework for secure boot, protected key custody, device identity, signing, attestation, and security policy enforcement. RISC-V’s quantum-safe silicon IP cores provide the underlying semiconductor building blocks that enable these capabilities in custom processors and SoCs.
Together, the two offerings give Synergy Quantum a vertically integrated approach that includes:
- Quantum-safe cryptographic hardware.
- RISC-V and SoC integration.
- Hardware-based identity and secure boot.
- Protected key lifecycle management.
- Attestation of device and workload.
- Trust services at the enterprise and infrastructure level.
This allows semiconductor developers to integrate quantum-safe hardware capabilities directly into their chips, while equipment manufacturers and infrastructure operators can deploy a broader end-to-end trust architecture through the SynQ Silicon Trust Suite.
“RISC-V gives semiconductor developers the flexibility to build processors and systems around their own requirements. Quantum-safe security should become part of that flexibility and be available as a native silicon capability rather than an afterthought added to the software layer. Synergy Quantum’s quantum-safe silicon IP cores are designed to help RISC-V developers implement post-quantum cryptography, secure boot, device identity and hardware-based trust directly into the SoC architecture integration.” – Jay Oberai, Founder, Synergy Quantum
Enabling sovereign quantum-safe semiconductor development
Ownership and control of cryptographic silicon IP is becoming increasingly important for governments, defense organizations, critical infrastructure operators, and semiconductor manufacturers. Synergy Quantum’s development of quantum-safe IP for RISC-V-based systems provides a foundation for locally controlled processors, secure controllers, communications equipment and mission platforms.
The use of configurable and auditable RISC-V architectures also allows developers to tailor security subsystems to national, industry and product-specific requirements. This can reduce dependence on fixed external cryptographic components while providing greater control over algorithm selection, security policies, and cryptographic lifecycle management.
About Synergy Quantum
Synergy Quantum develops quantum-safe platforms, cryptographic hardware and semiconductor security IP for governments, semiconductor companies, regulated enterprises and critical infrastructure operators. Her work includes post-quantum cryptography, RISC-V integrated quantum-safe IP, hardware roots of trust, cryptographic acceleration, quantum-safe connectivity, and crypto-agile infrastructure. The company’s mission is to protect the data, devices and networks that power modern civilization and build the trusted hardware foundation needed for the post-quantum age.
For more information, visit synergyquantum.in
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